Introduction and Motivation

The low energy (< 4 keV) quantum efficiency of a front side (FI) CCD is intimately related to the dimensions of the sub-pixel structures. The sub-pixel structures in question include the polysilicon gates and insulating layers, as well as channel stops: implanted P⁺ channels and their insulating layers. The gates run the length of the CCD, and are responsible for clocking the charge out of the device. The ACIS CCDs employ a three phase read-out scheme to transfer charge, so the gate structure is actually comprised of three different gates that differ slightly in dimension from one to another [Burke et al.1993]. Three neighboring gates define one pixel, with the boundary location dependent on the voltages applied to the gates. Figure 4.32 is an idealized schematic of a CCD cross section revealing the structure of the gates. Figure 4.33 is a SEM cross section of a CCD showing the over lap of gate B with gate A. The rectangular, black regions are the polysilicon gates. The white material over and between the gates is insulating SiO₂.

  

Figure 4.32: Gate structure of a CCD

The embedded channel stops run perpendicular to and lie beneath the gates. These structures help confine the charge clouds created by a photoelectric absorption and define the horizontal boundaries of a pixel. Figure 4.34 is a picture of a 2x2 array of pixels and shows the orientation of the gates and channel stops to one another. To fabricate the channel stops, a portion of the insulating Si₃N₄ layer is etched away. A P⁺ dopant is then implanted into the bulk silicon. Finally, the silicon is oxidized creating an insulating layer of SiO₂ between the channel stop and the gate structure. The gate structure is then grown on top of the silicon after this process. Figure 4.35 is a SEM measurement of a channel stop. The black and white bands at the top of the image are the polysilicon gates and insulating oxide, respectively. The elongated, hexagonal structure is the SiO₂ insulator between the P⁺ channel (not visible in this image) and the gates. The thin white structure between the gates and hexagonal insulator is the Si₃N₄.

  

Figure 4.33: SEM photo of the CCD gate structure. Gate B is shown overlapping gate A. The bar above the text in the photo is 1 $\mu m$.

  

Figure 4.34: Schematic of a 2x2 array of pixels showing the orientation of the gates and channel stops. The channel stops are beneath the gates.

  

Figure 4.35: SEM measurement of a channel stop

When modeling the quantum efficiency of an ACIS CCD, the complicated gate structure can accurately be approximated as uniform slabs of material that cover the entire CCD. This model assumes that the charge created by a photon interaction in one of these layers is not collected by the device (i.e. the layer is ``dead''). This model-The Slab and Stop model-was first developed by Keith Gendreau during calibration of the ASCA SIS CCDs [Gendreau1995]. The Stop part of the model refers to treating the hexagonal insulator structure and implanted P⁺ as rectangular regions of dead SiO₂ and Si, respectively. The absolute calibration of the reference standards involves fitting the data obtained at the BESSY facility with the Slab and Stop Model. While the BESSY measurements determine the thicknesses of the gate slabs, they prove insufficient for constraining the channel stop parameters. Construction of a highly accurate CCD model, then, requires determination of this information in some other fashion.

Footnotes

See Section 4.6.1 for details.