EDA Import Dialog

The EDA Import Dialog is opened automatically when creating 3D simulation models from PCB/package layouts, or when using the functionality "Export to MWS..." from within CST PCB Studio.

After 3D-geometry generation, the dialog can be re-opened by right-clicking on a 3D PCB body (or folder) -> EDA Import Settings...

Background: EDA CAD tools normally provide layer-thicknesses data as 'effective', i.e. real layer thicknesses after manufacturing. Thus, the thickness of a substrate layer specifies the distance between attached copper layers in the physical PCB. As an effect of the manufacturing process, copper layers are somehow pressed into adjacent soft substrates (so-called Prepregs) whereas they are just glued on top of hard substrates (so-called Cores). It is the task of the PCB manufacturers to account for these effects by choosing the right raw substrates. In this way, the physical PCB will have the same dimensions as those given the CAD layer stack-up, as shown in the following picture (4-layer PCB by foil construction, solder mask neglected):

As can be seen, the filling of voids in the copper layers (which happens through flow processes from adjacent substrates during manufacturing) is not fixed by the given data. For that reason, these additional pieces of information can be supplied in the present dialog (see field 'Filling from' below). Naturally, the nature of substrates (Core/Prepreg) determines how the void filling happens: 1-from below, 2-from above, 3-from below, 4-from above:

In order to offer maximum flexibility, the substrate thicknesses can also be handled as 'raw', meaning that the effect of pressing in copper layers is considered explicitly here: The copper layers are pressed into substrates as specified in the 'Filling from' field, but the copper thicknesses do not contribute to the overall PCB thickness.

In this field, a pre-defined material can be chosen from the library. If set, the library material will override the settings made in the fields "Cond./tan delta" and "Permittivity".

For "lossy metal"-type layer, specifies the electrical conductivity in Siemens/m, for "dielectric" layers, specifies the loss angle (d) through tan(d). If the value of tan(d) is nonzero, the material model used in CST Microwave Studio® will be a first-order Debye model (Material Overview), which also requires the definition of the measurement frequency of the specified permittivity and tan(d). This frequency can be also specified in the present column using the syntax "0.02@1.5GHz", which means that the permittivity and tan(d)=0.02 are found at 1.5GHz. Please note that a zero frequency specified here will be replaced by the center of the frequency window defined in CST Microwave Studio®.

Thermal material settings are important for the thermal solvers of CST Mphysics Studio. Because the EDA input files do not contain any thermal material properties normally, some default values are assumed here (k=thermal conductivity in W/K/m, cp=specific heat capacity in kJ/K/kg, rho=density in kg/m^3):

Material properties can be changed later on in CST Microwave Studio (exception: see feature "Automatic PCB thermal model simplification" below).

Elevation of the layer above z=0. The column automatically updates itself when the user changes layer thicknesses, with the exception of layers inside a diestack. If the user changes the thickness of non-diestack layers, the elevation of diestack layers must be corrected manually.

This switch controls how the voids of copper layers are filled by adjacent substrate material. Options:

This switch controls the side, i.e. top or bottom, to which the etch factor (see below) applies. Top and bottom refer to the general stackup direction. Options:

The etch factor defines the skewness of the etch sides. The factor equals the ratio a/b as defined in the cross-sectional view of an arbitrary etch below. The height a is always equal to the layer thickness and b can be regarded as the shrink length w.r.t. the opposite side. The etch factor can only be positive.

When switched on the stack-up data is considered as 'effective', as opposed to 'raw', see the above background for an explanation of these terms.

This setting switches between various schemes that create equivalent solids in the 3D model after import with effective thermal properties. This may be used to reduce the computational complexity in thermal simulations. Averaging the material properties is based on the volume fraction of metal to dielectric. The actual volume fraction of metal to dielectric is displayed in the messages tab after import.

This setting can only be applied to the full design, i.e. net selections and area selections are not considered.

Note that some materials from the CST material library don't have all the required settings (thermal conductivity, heat capacity, density). Such materials can not be used for thermal model simplification. It is possible to complete the library materials in CST Mphysics Studio or to define new ones and then use these materials here.

lets you choose the length unit for layer thickness and elevation in the stack-up table (micrometers or mils).

Background: For the purpose of signal/power integrity simulations, a part is characterized by the following pieces of information: part number, pin list, and electromagnetic model. The former two are fixed within the design, whereas the latter can be customized by the user. Currently, only two-pin, passive parts are supported by the EDA import, corresponding to the Lumped Element model and the L-HF, R-HF models that can be defined in CST PCB Studio. For the case of resistors, inductors, or capacitors, the corresponding R, L, and C values are extracted from the PCB database, if present. Components, on the other hand, describe the placement of part items on the board (position, rotation, mount type, layer). They are addressed by their so-called reference designator (e.g. "R101", "L392", "C901").

The currently assigned part to the component. By right-clicking the part name, a context menu appears that allows to change or unset the current part assignment. Choosing change (or double-clicking) will launch the Part Library, from which a part can be chosen by selecting a part and clicking "OK". A third option called "Create missing RLC-part" is available when there are parts specified, that are not defined in the current part library. Choosing this option results in the creation of an RLC-part with invalid values, which the user needs to set manually.

A descriptive information text about the electromagnetic model pertaining to the part.

This is a plain text file, readable e.g. by Microsoft Excel. The .csv file should exhibit at least three columns with headers "refdes", "partname", and "value", separated by comma, semicolon, colon or tab character. Column "refdes" contains the component references (e.g. "R101"), column "partname" denotes the part IDs (manufacturer ID or enterprise-wide part ID), whereas the column "value" contains the lumped-element values (units are Ohms, nano-Henries, and pico-Farads). For correct interpretation of values, the respective types of components (R, L, or C) must be known. This type can be specified in an additional column, "type", containing one of 'R', 'L', or 'C'. If the "type" column is absent, the first character of the "refdes" will be used as type specifier.

Note: when using Microsoft Excel to view the .csv file, consider using the "Filter" option for easy sorting and filtering the table.

From Cadence Allegro PCB Editor, this text file can be produced by the report mechanism. In Cadence Allegro, please type "old_reports" in the command window. In the dialog box appears, select "Components" and specify the output filename (e.g. components.txt). Pressing "Report" will produce the file that can be loaded into the part editor.

This will open a new window providing access to the Part Library. The part library allows the user to build up a library of parts, which can be stored and loaded. Currently only 2-pin RLC and subcircuit parts are supported.

A descriptive information text about the electromagnetic model pertaining to the part.

To the right of the table, the embedded editor allows the user to change the values for a selected part. Depending on the part type, the following editors are available:

Under Type the underlying equivalent circuit can be chosen. For each type, except for 'short', the R, L and C values may be set. At least one of them must be non-zero for a valid setup.

The special case of a "Short" is used to represent elements of zero impedance, and will be imported as PEC wires or sheets (depending on the setup here).

Under Filename the file may be specified containing the model. Clicking the View button will show a dialog in which the content of the model file may be inspected.

For components with more than 2 pins and even number of pins (2n) an array of lumped elements will be created. The mapping from model pin to component pin will be done automatically according to the selected scheme under Array layout. Here, "1:n, 2:n-1, ..." adds a lumped element between opposite pins (a typical layout for surface-mount and through-hole components) and "deduce from pin geometry", which will automatically create lumped elements between component pins in a geometrical optimal sense.

There is also the possibility to set a Size code as a free string (not used in the 3D import).

Ability to load all parts from a previously stored CST Part Database library file (.dat).

The table needs to consist of exactly the columns partname, type, R, L, C (in that order). The allowed column separators are , ; : <TAB>.

Numerical values (columns R,L,C) are given in SI units, potentially followed by metric prefixes (f,p,u,m,k,M,G).

The type value must be one of the characters RLC, specifying which numerical value will be considered as the nominal value of the lumped element.

The other two numerical values denote the element parasitics, using the equivalent circuits:

Note: If there are conflicting part names, in a follow-up dialog, these parts can be replaced, skipped or added uniquely to the existing database.

Opens up a new window in which the user can specify a part name, and set its type: RLC or subcircuit. After clicking "Ok", define RLC values, or choose a subcircuit file.

If turned on (default) then the components get imported into CST Microwave Studio.

A preview of the PCB is displayed in this tab, with the intent that the user may graphically select a subset of the total board. For highly complex designs, treating the board as a whole may not be desirable due to simulation performance so that a selection procedure becomes mandatory.

Layer shapes can be displayed or hidden using this check box matrix. The rows of the matrix correspond to the conductor layers (layer name in the first column), where "*" means "all layers". The meaning of the columns if as follows:

Nets can be highlighted by selecting them, and net types ("sig", "pwr", "gnd") can be changed for one or multiple nets at a time. Columns "Sel.", "Name", and "Type" hold the selection state, name, and net type, respectively, for each net.

Please use the filtering option for restricting the list to the interesting nets.

Within this group of tools, the geometry to be imported into the 3D model can be restricted, in order to reduce simulation complexity (see example below).

Use this option to restrict the 3D model to the copper geometries contained within a defined area.

If checked, a selection rectangle or polygon may be drawn in the board view: right-click in the view window and select "New rectangular/polygonal selection". For rectangular selection, just left-click at one corner, draw the rectangle, then release the mouse button. For polygonal selection, left-click at the starting position of the polygon and add further points by additional left-clicks. In order to close the polygon, right-click and choose "Done" from the pop-up menu. When the grid option is turned on, all selected points will be snapped to the grid during the selection procedure (a polygon may now also be closed by clicking on the start position). Holding down the Shift-key will allow for purely horizontal, vertical and 45-degree selection.

Alternatively, a restriction area can be auto-generated around selected signal nets (traces), where the area contains all points within a given distance to the traces: When pushing the "Area" button, a pop-up dialog will query the user for this inclusion distance ("Include shapes within distance"). The option "Include power/ground nets" allows to include/exclude the supply nets into the area computation. The selected area can be simplified to its bounding rectangle with the option "Rectangular selection area".

After the selection area has been defined, a dialog will pop-up in which the user can specify for which layers the selection should be effective. Multiple selection areas may be defined for each layer and the selection areas may overlap. Clicking on a point belonging to an already defined polygon, will make the selection active. Right-clicking will bring up a pop-menu with the following options:

Remove point on polygon: Removes the selected point from the polygon.
Change layer selection: Brings up the layer selection dialog to modify previous selections.
Snap shape to grid: (re)snaps the selected polygon to the currently defined grid.
Delete selected polygon: removes the selected polygon.
Delete all polygons: deletes all selection polygons on all layers.

When creating the etch shapes from the traces, planes, and pad shapes, all geometries will be clipped to the selection area.

If checked, only shapes belonging to the selected electrical nets will be considered for import.

If checked, only selected layers will be considered for import. Pushing the button opens a layer-selection dialog.

Example (cross-talk between two signal nets): Select the coupled nets in the "Net Highlighting" window. Then, create a selection area around the two nets using the "Area" functionality. Now, if needed, also select reference nets (e.g. GND, VCC) and enable "Restrict to selected nets". The resulting 3D model will comprise the two signal nets and their reference planes, restricted to the selection area.

Manually defining many discrete ports in the 3D model may be time-consuming. Alternatively, discrete ports can be defined already in the EDA Import Dialog: By using the logical information contained in the layout (pins, nets), the present dialog offers a convenient means for generation the desired external connections needed for the simulation. In addition to the integer number of the ports, port labels are generated in the 3D model in order to identify the pin(s) a port is attached to.

In the dialog, the left-hand-side list displays all pins in the layout, including the respective component and net. This table can be sorted by each column, thus allowing to easily find all pins of a given net, for instance. The filtering option supports the navigation in the pin list.

As every pin corresponds to a predefined 3D position (normally on the surface of the layout), ports can be defined by connecting pairs of pins. Only pairs of pins of the same component are sensible to consider here. If N pins of a certain component are to be excited in the simulation, N-1 pin-to-pin ports are needed to completely characterize the situation. These N-1 ports form a spanning tree between the selected pins. If only a subset of all pins of the component are selected, it is easy to imagine that the horizontal wires forming the ports may intersect the pin-pads of unselected pins, thus leading to shorts. In order to prevent producing shorts, vertical wire leads are automatically added on top of the selected pins. The height of the leads can be manipulated in the separate dialog Specials...->Ports / Lumped elements

For generating pin-to-pin ports, one selects a set of pins in the pin list and presses the arrow button pointing to the "pin-to-pin ports" group on the right. The dialog will automatically construct the spanning tree(s) for each of the involved components. Flag "Invert Direction" exchanges the starting point and the endpoint of the discrete port. Ports can be deleted by selection and pressing the "delete" key. In the layout view, the ports will appear as blue arrows between pins.

As a second option for port generation, every selected pin can be connected to a close-by reference conductor (net or PEC sheet, see Specials...->Ports / Lumped elements).

For generating pin-to-reference ports, please select pins in the pin list an click the arrow button pointing to the "pin-to-reference ports" group on the right. Ports can be deleted by selection and pressing the "delete" key. Please note that, as a second step, it is mandatory to define the reference nets for each pin-to-reference port. Using multi-selection, the same reference net(s) can be assigned to all selected ports. In the layout view, the ports will appear as blue triangles.

Note: In the presence of a common reference net for all pins, the pin-to-pin and pin-to-reference approaches are equivalent, as voltage differences between two pins can either be expressed through the voltage difference between the associated pin-to-reference ports, or through the sum pin-to-pin ports that connect the two pins within the spanning tree. If no reference conductor can be identified, or its physical meaning is questionable, using pin-to-pin ports is recommended, since this approach correctly reflects the voltage differences seen by the external component.

For low-frequency or static simulations, current ports and electrical potentials can be created automatically, here, for selected PCB pins. In order to geometrically define such an excitation at a given pin, a small circular PEC sheet will be added at the pin position, the size of which is governed by these parameters. For an overview of sources supported by CST EM Studio, see here.

For generating current ports, please select some pins in the left panel and click on the arrow button pointing to the "Current ports" panel on the right. Selected ports can be deleted by pressing the "delete" key, or by using the opposite-arrow button. For the meaning of the individual column settings, see here. In the layout view, the ports will appear as turquoise triangles.

Potentials can be created similarly to current ports. For the meaning of the right-hand-side columns, see here.

In addition to the pin-based port definition, one can also define the start and end positions of a port graphically within the layout view. Here, we differentiate between two types of discrete ports:

vertically-oriented port (directed along z axis): By right-clicking in the layout view window, and choosing "Add vertical discrete port here...", a vertical port can be defined at the position of the mouse right click.
port with general orientation: By right-clicking in the view window, and choosing "Add general discrete port from here...", a discrete port with arbitrary start and end points can be defined, where the start point is given by the position of the mouse right click. The end point is defined by the next left-click.

After that, a dialog box appears that displays the current port number and two identical lists of the conductor layer names. The start layer (first list) and end layer of the port (second list) can be selected here (they have to differ in the vertical case). Clicking "OK" finishes the port definition. The lower tip of a blue triangle now indicates the location of the port.

This feature allows automatic creation of volume heat sources based on component outlines. For this select desired components in the left panel and click on the arrow button pointing to the "Heat sources" panel on the right. Please enter on the right the power and height of the volume heat source. Heat sources can be deleted by selection and pressing the "delete" key.

"Project": Import component losses from CST PCB Studio IR-drop results. Also sets the field "Import thermal losses from CST PCB Studio Project" (see below).
"irdrop_0Dresults.xml": Import component losses from CST PCB Studio IR-drop results. The file is typically stored in the subfolder "Result\IRDROPRESULTS" of an existing CST PCB Studio Project, once results have been computed.
"Csv File": Import heat sources from ASCII file. The file should contain three columns, refdes, power and height, separated by a common delimiter (comma, semi-colon, tab, etc.). A header is optional.

Imports distributed losses computed by a CST PCB Studio Project containing IR-Drop simulation results.

For each layer selected for import, unite all conductor shapes (traces, plane shapes, and pads), if desired, restricted to the selected area and/or nets. The generated etch shapes correspond to the physical copper shapes and do not differentiate between the original shape types. However, net information is kept in etch shapes. The result is the set of shapes that will appear in the 3D model. In the layout view, these shapes can be displayed by activating the column "E" in the Layer Visibility matrix.

Pressing this button runs a number of checks on the portion of the layout that will be imported into CST Microwave Studio. In order to carry out the checks, the merged copper shapes (etch), need to be present (press "Preview" button). The check results will be displayed in separate tabs near the "Net highlighting" tab. (Please use the window handle between the tabular and graphical view to extend the table section.)

This check may unveil geometrical artifacts that can lead to problems of the 3D model. Particularly in the case of tetrahedral meshing, these artifacts may render mesh generation very slow or even impossible. The artifacts described below are noted in the table. Every entry can be displayed by checking its visibility flag ("Vis.") and enabling its view in the Layer visibility section (column "show problem markers"). In order to look at the individual artifact entries, it is recommended to also switch on the etch display in the Layer visibility section. The column "Sel." can be used to select particular entries for quick filtering using the "Filter:" editbox. Columns "Type", "Layer" and "Remark" contain the type, the layer name and additional information for the respective geometrical artifact. The following types of geometrical artifacts may be detected:

Two very close segments that do not intersect create a tiny gap. In case of tetrahedral mesh generation, this gap needs to be bridged, in turn leading to overly strong refinement around that place. In some cases this artifact may even reflect true layout errors because metal connectivity may be fragile.

This artifact arises if a via scratches the boundary of an etch shape. For meshing, this is often uncritical, but it still indicates a layout problem: For connectivity reasons, vias normally end in the middle of an etch shape (e.g., a pad), without scratching its boundary.

self-intersecting / self-touching / self-overlapping / segments-disconnected contour

The shape contour intersects / touches / overlaps itself or has disconnected segments. A combination of these geometrical artifacts may be reported for a single contour.

Narrow gap between boundaries of two separate shapes. To heal detected sliver gaps, check the option Specials... > General > Heal sliver gaps and press "Preview" button again.

In addition, the table may contain information about automatically healed geometry artifacts including healed close edges, healed sliver gaps and healed self-intersections.

Analysis of connectivity between pins. Please note that a component pin is defined as a 3D point having a name and a net. If the PCB connectivity is correct, exactly all pins of the same net are connected (thus forming a group). The result of the pin-connectivity check is displayed in the tab "Connectivity report": Columns "Refdes", "Pin", and "Net" denote the respective component name, pin name, and net. Column "Function" contains the word "port" for pins with a port attached to them and "ref. net" for pins connected to a reference net. Column "Group" displays the number of the connectivity group the pin belongs to. Please note that this number is an arbitrary identifier for each group. Column "Remark" contains information of errors in connectivity, with the cases:

Parameters referring to length scales of copper shapes may be edited/inspected in this dialog.

If checked, PCB etch shapes will be represented as 3D solids of small, but non-zero thickness.

If checked, PCB etch shapes will be represented as 2D sheets instead of 3D solids.

Determines the smallest relevant length of shape segments. Smaller segments will be eliminated upon cleaning, thus smoothing the respective etch shape (see background below). This length can also be considered as the supposed etch (xy) manufacturing tolerance. Default value is one micron.

If checked, unconnected (sometimes termed "unused") pads will be excluded from etch creation (and thus from the 3D model). It is possibly to choose between the following algorithms:

A pad is unconnected if it does not touch any other etch shape lying on the same layer. An unconnected pad is suppressed if it is not on the start or end layer of a drill (no matter if through-hole or blind/buried via).

Remove unused pads on Split/Mixed Planes (mainly for Mentor Graphics PADS Import). A pad is unconnected if it does not touch any other etch shape or touch shape from different net lying on the same layer. All pads on top and bottom layers remain unchanged.

In Zuken PCB designs, pads are assigned attributes reporting their connectivity state. Enabling the current option, pads of type 'Noconnect' will be dropped when creating the 3D model.

Notes: If the flag for "Remove unused pads" is already activated in the PADS ASCII-File, the PCB-Import Dialog will get this information and use the appropriate algorithm.

If checked (and restriction to selected nets is active), a copper shape from an unselected net will be included if it overlaps a shape from a selected net.

If checked, overlapping nets will be reported to the user, and the user may choose which net name to use for the 3D body. If unchecked, each net will be translated into an independent 3D body.

Background: An essential feature of the CST EDA import is the automatic cleaning and healing procedure performed upon setting up the 3D model. In that way, the shape complexity of the model is reduced, leading to better performance of 3D electromagnetic simulations. By modifying the parameters discussed here, the user may directly take influence on the cleaning and healing algorithm. For additional settings of the cleaning and healing algorithm see Healing and simplification.

If unchecked, soldermask layers will be represented in the 3D model by a dielectric brick similar to the substrate layers. Some EDA formats, however, support the specification of the cutouts inside the soldermask. In a real PCB, these cutouts are needed around component pads, in order to ensure that the pads are not covered by soldermask. If, in contrast, this was the case, component mounting (soldering) would be error prone. Hence, if the imported layout contains the corresponding data, checking the current setting will generate the cutouts within the soldermask in the 3D model.

If checked (in the case that only a part of a PCB is imported using area selection), the substrate layers will be forced to be of axis-aligned, rectangular shape, irrespectively of the shape of the section area. The resulting rectangle will be minimum, but containing the selection area (also see the next option).

If the 'axis-aligned bounding box' option is checked, the rectangular substrate layers will be extended laterally by the distance specified here. Extending the substrate layers by a small amount using the present option can facilitate the mesh generation process for tetrahedral meshes.

In reality, the solder-mask covers the top PCB layer in a way that conforms to the present etch shapes. This is due to the solder-mask being a lacquer-like material that 'paints' the PCB outer side. Below, this observation is visualized in a cross-section view for two cases (neglected or considered etch-factor, see above).

Algorithmically, the top and side faces of the etch shapes are extruded along their outward normals by the solder-mask thickness. This results in new 3D body that appear thickened w.r.t. original etch shapes. These bodies are considered as soldermask material and are united with the existing planar solder-mask sheet.

When choosing the option "For signal nets" the above -potentially time-consuming- algorithm is only applied to the etch shapes of net type "signal". Please note that this is the most relevant case because signal-trace impedances need to be characterized with higher accuracy than those of power/ground nets. In contrast, the option "For all nets" enables the conformal-solder-mask algorithm for all etch shapes on the outer layers, irrespectively of their nets.

Sometimes, layout designs carry the convention that drill-hole diameters need not be specified explicitly, but can be taken from the set of pads that belong to the same padstack as the drill-hole. When checking this option, drills of diameter zero will be corrected to the smallest pad diameter contained within the padstack.

If only a subset of layers is imported into 3D (see 'Restrict to selected Layers'), vias may exhibit stubs. Switching on the present option will trim the via stubs to the layer span that is actually present.

Many layout designs consider vias as finished holes, i.e. as drilled holes that were plated. Therefore, the finished holes have a radius equal to the drilled holes, decreased by the plating thickness. In principle these vias are hollow tubes. In CST Microwave Studio, these vias are represented as solid cylinders with the diameter of the finished hole. If checked, the user has the ability to slightly increase the via radii by the plating thickness in um, such that the via radii become equal to the drill-hole radii.

Automatic application of effective via material for solid vias, such that their resistance equals that of the hollow via of the original material.

The following quantities are considered: Drill diameter, d, and plating thickness, t. For all material coefficients considered, the scaling factor is given by the ratio of cross-section areas between solid and hollow via.

In this way the following material properties will be scaled: "electrical conductivity", "thermal conductivity" and "material density".

Set value for via material. This option is only visible by import to MPhysics Studio instead of "Electric conductivity".

In order to keep the model complexity low, bondwire cross sections are always approximated by a chain of straight segments, see the following figure. The present field determines their number.

If two bondwires meet at a point (s. left figure below), the local geometric complexity of the 3D model will increase, as more surface shapes are needed to correctly model the junction. This can be avoided by slightly separating the bondwires' end points. The present factor determines the distance of this separation in terms of the mean radius of the two bondwires. The result in the 3D model is shown in the right picture below. (This modification is restricted to angles<p/2 between bondwires).

Flat incidence of bondwires causes a large footprint on the substrate, as shown in the left picture below. In the worst case, shorts between neighboring bondwires may occur, invalidating the 3D model. In order to avoid the problem, a small vertical segment is added, so that the bondwire footprint becomes minimum (see right figure). The vertical segment will be added if either the incidence angle is smaller than the given minimum or the footprint is larger than the specified, absolute length. The length of the segment will be the lift factor times the radius of the bondwire.

This table allows for the adjustment of the top, center and bottom radius for all bump and BGA solder balls in the design, see picture below. Please note that the solder-ball geometry will in general be a rotated spline. If all radii are identical, solder balls will be modeled as cylinders. All sizes are given in micrometers (um).

This option defines the distance of component pins to the respective mounting layer. When unchecked, discrete ports and lumped elements will connect pins directly on the surface of top/bottom conductor layers, thus potentially leading to shorts in the presence of a third net passing in between the pins. When checked, discrete ports and lumped elements will be attached to the component pins by additional, vertical leads.

for surface and embedded components with a height value: the middle of component height.
for surface components without a height value: the outer elevation of the attached solder mask.
for embedded components without a height value: the middle of the attached dielectric layer.

Using this option, vertical leads are created vertically with an explicit user-defined length.

The search for the reference point is carried out in the 3D geometry in order to make sure that the connections are valid, see the next figure. An important requirement for port validity is that the port edge does not intersect or touch other conductors. This is checked within a geometrical tolerance given by the parameter Specials... > Mesh > lateral reference length (see below). The respective search algorithm may shift the pin position to the boundary of the pad if adequate.

This parameter specifies the maximum length of this kind of pin-to-reference ports and has been introduced to prevent long computation times in case of failing reference-conductor search.

This option will introduce PEC sheets for all components for which ports have been specified. PEC sheets are perfectly-conducting sheets of about the size of the component footprint, that are always placed directly above or below the component's pins. Ports (and shorting wires) are then attached from the pins to the PEC sheet vertically. The PEC sheets are placed at a distance to the component pins, specified by the pin-lead height. To avoid problems inside diestacks, the distance to the pins is the minimum of the user-defined pin-lead height and half the die-layer thickness. If any reference nets are specified in the ports dialog, then the pins with corresponding nets will be shorted to the PEC sheet. Note that it is also possible to select specific pins for port creation, without defining reference nets. However, as the PEC sheet acts as a local reference, at least two connections to the PEC sheet are needed.

This option is similar to the previous one, except for the creation of face ports instead of edge ports.

Choosing In-plane will result in circular face ports lying in the PEC-sheet. Choosing Vertical will result in vertical flat face ports.

A pin-to-pin port can be geometrically represented in one of the following ways.

The two pins of the lumped element are directly connected by an edge representing the lumped element. If the component elevation is non-zero, vertical pin-leads are used and the lumped-element edge is lifted accordingly.

This is option is similar to the one before, but the construction happens through two-dimensional rather than one-dimension objects.

The lumped element is represented by a vertical edge lumped element and a shorting wire both connecting to the component PEC sheet (see above).

If this control is checked, all lumped elements that are defined as ideal shorts (see here), will be imported as a real resistance R as specified in the edit field. If the control is unchecked, all ideal shorts will be imported in the shape of small PEC wires or sheets (depending on the geometry defined above).

The reason for providing this option is that shorts represented as PEC wires or faces do not allow adding voltage/current monitors.

This option will introduce a PEC-sheet below (or above) the BGA at a distance specified by the pin-lead height. All component pins that have a net class equal to GND will be shorted to this PEC-sheet.

Parameters allowing to influence the predefined mesh settings for imported shapes.

The imported PCB solids will carry predefined mesh settings. For the computation of the density of mesh lines in x and y directions the present length is used as a reference, see the following option.

The present option allows to set the size of the minimum x/y mesh step relative to the lateral reference length ("coarse":2, "medium":1.0, "fine": 0.7). User-specified values different from the predefined ones are also allowed. Please note that global mesh settings may override these settings (e.g. the "Mesh line ratio limit" for hexahedral meshes).

For hexahedral meshes, the EDA import process will add mesh lines at the top and bottom side of each substrate layer. This enforces the presence of horizontal mesh lines within every conductor layer. In order to improve the mesh resolution within the substrate layers, additional mesh lines can be introduced by choosing values larger than zero in the present option. Again, the global mesh settings may override these settings (e.g. the "Mesh line ratio limit" ).

In the default unchecked state, the die-bricks will not be considered for simulation.

Create 3D component outline if the component has a height value. It is only for visualization, will not be used for simulation. Visible only if import contains component height information.

Parameters allowing to tune the automatic cleaning and healing procedure performed upon setting up the 3D model.

The tolerance of algorithms used to detect and heal geometrical artifacts is equal to the tolerance coefficient multiplied by the PCB tolerance. If the tolerance coefficient is set to 0, the tolerance is selected automatically.

If not checked, only close segments in circular outlines of etch shapes are healed. If checked, close segments in circular holes of etch shapes as well as short segments are healed additionally.

If checked, detected narrow gaps between boundaries of two separate shapes are healed.

To view the list of healed geometrical artifacts, press "Check" button and switch to the "Layout problems" tab. Healed geometrical artifacts will be included in the list as "healed close edges", "healed sliver gap" and "healed self-intersection" entries. Note that the healing algorithm may fail to heal some of geometrical artifacts which will be listed without the "healed" prefix.

This option allows to configure the automatic creation of small circular PEC sheets for defining current ports and potentials. Please note that for the case of a through-mount device, where the pin position is located inside a drill hole, the PEC sheet will be identical to the drill hole.

This parameter specifies the minimum lateral distance between a PEC sheet and a 3D-body edge, relative (in percent) to the distance between pin position and edge.

Activate pan mode (if not in pan mode, panning works with the middle mouse button).

Transparency control for non-selected objects (applies to etch shapes only). Selected nets are always displayed with zero transparency. Hiding/unhiding layers changes the transparency for optimum visibility of selected objects (with the exception of transparency ="0% (fixed)").

[...] matches any single character defined in the character set, e.g. [abcDed] or [0-9]

| (vertical bar) for combining multiple expressions through logical "or", e.g. *gnd*|ground*|vss?

If the preview of the PCB is rendered with artifacts, for example, when using a remote desktop connection, close the EDA Import Dialog, select "File: Options" in the ribbon and enable the "Use software renderer for 3D views" check box in the "Preferences" tab. The EDA Import Dialog will use the software renderer when reopened. Please note that this check box is a global setting for all 3D views, uncheck it to enable the hardware acceleration by the GPU again.

The cylindrical bending of the 3D PCB is supported if bending instructions can be read in from the design file (currently supported: Cadence Allegro).

Pressing

in the preview window will open a table where each row corresponds to one bending instruction, columns having the following meaning:

The bend-cylinder center axis is above (below) the top (bottom) of the PCB by this distance

The bend regions and bend lines (center of bend regions) are shown in the graphical view while the table is open. Selecting a row in the table will highlight the corresponding bend in the display.

Changing parameters in the table is reflected by corresponding graphical changes in the view.

Stackup-regions are often defined in connection with bending. In the flexible part, less layers are typically used, and different rigid parts of the PCB may consist of a different number of layers.

Pressing

in the preview window will open a table where each row corresponds to one stackup region, columns having the following meaning:

The stackup regions are shown in the graphical view while the table is open. Selecting a row in the table will highlight the corresponding region in the display.

Please note that the specification of layer characteristics, as given in the stackup tab, is valid in all stackup regions as long as a given layer is part of that region.

Solder-masks (if present) are always added on top of the individual regions in the 3D geometry.