Unresolved Issues: Bias Stability

 An unexplained bias distortion invariably beginning at the start of a science run and enduring for hundreds of readout frame times has resulted in much consternation over worthless data and the current implementation of the prophylactic regimen with the charming sobriquet "jitter-dacs" which has become a permanent feature of the flight software. The distortion is clearly produced by an excess of charge which is only accrues when the parallel clock low level does not go below some near 0 volt level for a period of time equal to or greater than a single frame readout cycle. It is possible to believe that the sources of the charge are surface states lying directly under the gates, or at the gate-silicon junctures. Bringing the gate voltage low (or more precisely, jittering the voltage many times between high and low) depletes these states once and for all time. While this may be difficult to believe it is uncontested that without jitter-dacs neither useful data or bias can be acquired for long times after start of a science run.