From dd@spectra.mit.edu Tue Sep 14 23:52:05 1999 Return-Path: Received: from space.mit.edu (SPACE.MIT.EDU [18.75.0.10]) by wiwaxia.mit.edu (8.9.3/csr-2.4) with ESMTP id XAA21120; Tue, 14 Sep 1999 23:51:48 -0400 (EDT) Received: from spectra.mit.edu (SPECTRA.MIT.EDU [18.75.0.91]) by space.mit.edu (8.9.3/csr-2.4) with ESMTP id XAA25699; Tue, 14 Sep 1999 23:50:59 -0400 (EDT) Received: (from dd@localhost) by spectra.mit.edu (8.9.3/csr-2.4) id XAA08569; Tue, 14 Sep 1999 23:50:55 -0400 (EDT) Date: Tue, 14 Sep 1999 23:50:55 -0400 (EDT) From: Dan Dewey
Message-Id: <199909150350.XAA08569@spectra.mit.edu> To: ahicks@mit.edu, baluta, buehler, cal@head-cfa.harvard.edu, davis, dd, denicola, dph, dsd, fangt, gea, hermanm, houck, jcm@urania.harvard.edu, jhk, kaf, matumoto, mikstage, nss, pgf, pmo, staylor, wise Subject: pix_corner_lsi.par Status: R Content-Length: 8931 HETG and Cal Folks and Jonathan, Attached is an edited version of pix_corner_lsi.par. As indicated in the header the ACIS-S chips have been offset from their previous designed location to locations which cause the plus and minus orders of the HETG to coincide. S0-S5 have been offset by the following pixel values: -4.97, -3.58, -2.42, 0, -0.08, +0.33 Note that S3 remains fixed in location (except for correcting a typo in its location.) In determining these offsets it appears that the HEG and MEG zero-order locations are slightly offset with respect to the measured MEG+HEG zero-order location. The offsets above are independant of this. The effect of the zero-order offsets will have to be included in the Level 1.5 processing. The offsets are: HEG zero-order offset = +0.36 pixels MEG zero-order offset = -0.08 pixels Thus, e.g., HEG wavelengths on the positive side will have to be decreased by 0.36*0.00556 A after nominal analysis with the new pix_corner_lsi.par file, etc. Error bars on these offsets is +/- 0.2 pixels. Finally, I note that pix_pixel_plane.par has the value of an ACIS pixel as 0.0240040 mm - shouldn't this be 0.0240000 ??? (in two places.) It would be good to test these changes by reprocessing a Capella in-focus OBSID 1099 or 1235. Ideally the HR1099 data now being taken will also be processed with these values. Dave H will you be the lead on testing this? Cal group: any problems in "moving" the ACIS-S chips by these offsets? FYI, I note that Mark Bautz had provided the following "Y error" values (converted to pixels and with S3 fixed): -2.49, -2.14, -1.80, 0, -0.75, -1.23 It is possible these will depend on ACIS temp... HR1099 should provide a very useful check, Dan D ################### LSI to CPC corners definition file ############## # Chip Corner LSI coords of ACIS, HRC-I, HSI, and ACIS-2C in mm # # # # Chip CPC XMAX CPC YMAX # # Corner LSI X LSI Y LSI Z # # # # Reference: Tables 14-17, "ASC Coordinates", July 31, 1996 version # ###################################################################### # 1999-09-14 dd: # i) change typo in ACIS-S3-LR and 'UR: 18.451 --> 18.541 # ii) change typo in ACIS-S4-LR and 'UR: 0.208 --> 0.203 # iii) change the ACIS-S* Y values by offsetting them by # the offsets in $CALDBaxafcal/acis/cip/acisD1999-07-23tdetoffN0002.rdb # New left and right chip locations are: # Left: # -81.170 -56.133 -31.100 -6.0350 18.970 43.986 #Right: # -56.597 -31.559 -6.5240 18.541 43.545 68.560 # from $CALDBaxafcal/hetg/software/ddidl/marx/pix_corner_changes.990914.pro ###################################################################### ACIS,s,a,"CORNERS AXAF-LSI-1.0/ACIS-I&S&C AXAF-CPC-1.0",,, #====================================================================# # ACIS-Title,s,a,"ACIS-I/S (AI1) LSI coordinates (mm)",,, ACIS-chip-size,s,ql,"(1024, 1024)",,," ACIS chip size (x, y) in pixel" # ACIS-I0-LL,s,ql,"( 2.361 -26.484 23.088 )",,,"LSI coords for ACIS-I0 LL" ACIS-I0-LR,s,ql,"( 1.130 -26.546 -1.458 )",,,"LSI coords for ACIS-I0 LR" ACIS-I0-UR,s,ql,"(-0.100 -2.001 -1.458 )",,,"LSI coords for ACIS-I0 UR" ACIS-I0-UL,s,ql,"( 1.130 -1.939 23.088 )",,,"LSI coords for ACIS-I0 UL" # ACIS-I1-LL,s,ql,"( 1.130 23.086 -1.458 )",,,"LSI coords for ACIS-I1 LL" ACIS-I1-LR,s,ql,"( 2.360 23.024 23.088 )",,,"LSI coords for ACIS-I1 LR" ACIS-I1-UR,s,ql,"( 1.130 -1.521 23.088 )",,,"LSI coords for ACIS-I1 UR" ACIS-I1-UL,s,ql,"(-0.100 -1.459 -1.458 )",,,"LSI coords for ACIS-I1 UL" # ACIS-I2-LL,s,ql,"( 1.130 -26.546 -1.997 )",,,"LSI coords for ACIS-I2 LL" ACIS-I2-LR,s,ql,"( 2.361 -26.484 -26.543 )",,,"LSI coords for ACIS-I2 LR" ACIS-I2-UR,s,ql,"( 1.130 -1.939 -26.543 )",,,"LSI coords for ACIS-I2 UR" ACIS-I2-UL,s,ql,"(-0.10 -2.001 -1.997 )",,,"LSI coords for ACIS-I2 UL" # ACIS-I3-LL,s,ql,"( 2.361 23.024 -26.543 )",,,"LSI coords for ACIS-I3 LL" ACIS-I3-LR,s,ql,"( 1.131 23.086 -1.997 )",,,"LSI coords for ACIS-I3 LR" ACIS-I3-UR,s,ql,"(-0.100 -1.459 -1.997 )",,,"LSI coords for ACIS-I3 UR" ACIS-I3-UL,s,ql,"( 1.13 -1.521 -26.543 )",,,"LSI coords for ACIS-I3 UL" # ACIS-S0-LL,s,ql,"( 0.744 -81.170 -59.170 )",,,"LSI coords for ACIS-S0 LL" ACIS-S0-LR,s,ql,"( 0.353 -56.597 -59.170 )",,,"LSI coords for ACIS-S0 LR" ACIS-S0-UR,s,ql,"( 0.353 -56.597 -34.590 )",,,"LSI coords for ACIS-S0 UR" ACIS-S0-UL,s,ql,"( 0.744 -81.170 -34.590 )",,,"LSI coords for ACIS-S0 UL" # ACIS-S1-LL,s,ql,"(0.348 -56.133 -59.170 )",,,"LSI coords for ACIS-S1 LL" ACIS-S1-LR,s,ql,"(0.099 -31.559 -59.170 )",,,"LSI coords for ACIS-S1 LR" ACIS-S1-UR,s,ql,"(0.099 -31.559 -34.590 )",,,"LSI coords for ACIS-S1 UR" ACIS-S1-UL,s,ql,"(0.348 -56.133 -34.590 )",,,"LSI coords for ACIS-S1 UL" # ACIS-S2-LL,s,ql,"( 0.096 -31.100 -59.170 )",,,"LSI coords for ACIS-S2 LL" ACIS-S2-LR,s,ql,"(-0.011 -6.524 -59.170 )",,,"LSI coords for ACIS-S2 LR" ACIS-S2-UR,s,ql,"(-0.011 -6.524 -34.590 )",,,"LSI coords for ACIS-S2 UR" ACIS-S2-UL,s,ql,"( 0.096 -31.100 -34.590 )",,,"LSI coords for ACIS-S2 UL" # ACIS-S3-LL,s,ql,"(-0.011 -6.035 -59.170 )",,,"LSI coords for ACIS-S3 LL" ACIS-S3-LR,s,ql,"( 0.024 18.541 -59.170 )",,,"LSI coords for ACIS-S3 LR" ACIS-S3-UR,s,ql,"( 0.024 18.541 -34.590 )",,,"LSI coords for ACIS-S3 UR" ACIS-S3-UL,s,ql,"(-0.011 -6.035 -34.590 )",,,"LSI coords for ACIS-S3 UL" # ACIS-S4-LL,s,ql,"( 0.026 18.970 -59.170 )",,,"LSI coords for ACIS-S4 LL" ACIS-S4-LR,s,ql,"( 0.208 43.545 -59.170 )",,,"LSI coords for ACIS-S4 LR" ACIS-S4-UR,s,ql,"( 0.208 43.545 -34.590 )",,,"LSI coords for ACIS-S4 UR" ACIS-S4-UL,s,ql,"( 0.026 18.970 -34.590 )",,,"LSI coords for ACIS-S4 UL" # ACIS-S5-LL,s,ql,"( 0.208 43.986 -59.170 )",,,"LSI coords for ACIS-S5 LL" ACIS-S5-LR,s,ql,"( 0.528 68.560 -59.170 )",,,"LSI coords for ACIS-S5 LR" ACIS-S5-UR,s,ql,"( 0.528 68.560 -34.590 )",,,"LSI coords for ACIS-S5 UR" ACIS-S5-UL,s,ql,"( 0.208 43.986 -34.590 )",,,"LSI coords for ACIS-S5 UL" # # ACIS-2C are updated on 9/5/97 ACIS-C0-LL,s,ql,"( 0.0 47.57 11.10 )",,,"LSI coords for ACIS-C0 LL" ACIS-C0-LR,s,ql,"( 0.0 22.99 11.10 )",,,"LSI coords for ACIS-C0 LR" ACIS-C0-UR,s,ql,"( 0.0 22.99 -13.48 )",,,"LSI coords for ACIS-C0 UR" ACIS-C0-UL,s,ql,"( 0.0 47.57 -13.48 )",,,"LSI coords for ACIS-C0 UL" # ACIS-C1-LL,s,ql,"(-0.342 -15.18 10.45 )",,,"LSI coords for ACIS-C1 LL" ACIS-C1-LR,s,ql,"(-0.342 -39.76 10.45 )",,,"LSI coords for ACIS-C1 LR" ACIS-C1-UR,s,ql,"(-0.342 -39.76 -14.13 )",,,"LSI coords for ACIS-C1 UR" ACIS-C1-UL,s,ql,"(-0.342 -15.18 -14.13 )",,,"LSI coords for ACIS-C1 UL" # # HRC,s,a,"CORNERS AXAF-LSI-1.0/HRC-I&S AXAF-CPC-1.0",,, # #====================================================================# # #Updated on 12/24/97 HRC-Title,s,a,"HRC LSI coordinates (mm)",,, HRC-I-chip-size,s,ql,"(16384, 16384)",,,"HRC-I chip size (x, y) in pixel" HRC-S-chip-size,s,ql," ( 4096, 16456)",,," HRC-S1 & S3 chip size (x, y) in pixel" HRC-S2-chip-size,s,ql,"( 4096, 16456)",,,"HRC-S2 chip size (x, y) in pixel" # HRC-I-LL,s,ql,"(0.0 0.000 74.482 )",,,"LSI coords for HRC-I LL" HRC-I-LR,s,ql,"(0.0 74.482 0.000 )",,,"LSI coords for HRC-I LR" HRC-I-UR,s,ql,"(0.0 0.000 -74.482 )",,,"LSI coords for HRC-I UR" HRC-I-UL,s,ql,"(0.0 -74.482 0.000 )",,,"LSI coords for HRC-I UL" # HRC-S1-LL,s,ql,"(2.644 161.949 -13.167 )",,,"LSI coords for HRC-S1 LL" HRC-S1-LR,s,ql,"(2.644 161.949 13.167 )",,,"LSI coords for HRC-S1 LR" HRC-S1-UR,s,ql,"(0.000 56.180 13.167 )",,,"LSI coords for HRC-S1 UR" HRC-S1-UL,s,ql,"(0.000 56.180 -13.167 )",,,"LSI coords for HRC-S1 UL" # HRC-S2-LL,s,ql,"(0.000 56.180 -13.167 )",,,"LSI coords for HRC-S3 LL" HRC-S2-LR,s,ql,"(0.000 56.180 13.167 )",,,"LSI coords for HRC-S3 LR" HRC-S2-UR,s,ql,"(0.000 -49.622 13.167 )",,,"LSI coords for HRC-S3 UR" HRC-S2-UL,s,ql,"(0.000 -49.622 -13.167 )",,,"LSI coords for HRC-S3 UL" # HRC-S3-LL,s,ql,"(0.000 -49.622 -13.167 )",,,"LSI coords for HRC-S2 LL" HRC-S3-LR,s,ql,"(0.000 -49.622 13.167 )",,,"LSI coords for HRC-S2 LR" HRC-S3-UR,s,ql,"(2.253 -155.400 13.167 )",,,"LSI coords for HRC-S2 UR" HRC-S3-UL,s,ql,"(2.253 -155.400 -13.167 )",,,"LSI coords for HRC-S2 UL" # HSI,s,a,"CORNERS AXAF-LSI-1.0/HSI AXAF-CPC-1.0",,, # #====================================================================# # HSI-Title,s,a,"HSI LSI coordinates (mm)",,, HSI-chip-size,s,ql,"(4096, 4096)",,,"HSI chip size (x, y) in pixel" # HSI-LL,s,ql,"(0.000 -13.17 -13.17 )",,,"LSI coords for HSI LL" HSI-LR,s,ql,"(0.000 13.17 -13.17 )",,,"LSI coords for HSI LR" HSI-UR,s,ql,"(0.000 13.17 13.17 )",,,"LSI coords for HSI UR" HSI-UL,s,ql,"(0.000 -13.17 13.17 )",,,"LSI coords for HSI UL" # mode,s,h,"h",,,